• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    In a multi-port memory system having a plurality of ports for data input and output, a plurality of memory banks, and a switching network for connecting each of the ports to each of the memory banks, the improvement wherein a page address is transferred over a data line of the switching network and is set, address computation is effected on the side of the memory banks, and the data are read out continuously from the plurality of ports and are written on the same page.
    公开号:SU1561834A3
    申请号:SU874202747
    申请日:1987-06-12
    公开日:1990-04-30
    发明作者:Екота Харуо
    申请人:Япония, Представленная Генеральным Директором Агентства Промышленных Наук И Технологии (Фирма)；
    IPC主号:
    专利说明:

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    Moreover, since the transfer of the address to the next memory bank and the access to the memory from the port can be performed simultaneously independently of each other, data can be read and recorded in contiguous areas without an excessive increase in their sampling time. A buffer block made between the port and the switch
    The invention relates to computing, in particular to multiport memory systems, and can simultaneously perform paging samples from a number of identical or different processors or disk systems, each of which contains a magnetic disk memory and a controller.
    The aim of the invention is to reduce hardware costs and increase speed by transferring the page address from the data lines and calculating the internal page address for each memory block separately.
    FIG. 1 shows a functional diagram of the proposed device; in fig. 2 - functional diagram of the address driver; in fig. 3 is a diagram of a memory block; in fig. 4 - time diagrams of the device; in fig. 5 is a diagram of the distribution of blocks and pages in the memory blocks.
    The device (Fig. 1) contains a counter 1, a switch 2, a group of register ports 3 (P0-P150, a group of memory blocks 4 (MB0-MB 5), a group of address formers 5, a group of buffer memory blocks 6 (PBO- PB 5) and clock input 7 (from the output of the master oscillator device).
    The address generator (FIG. 2) contains a counter 8, a memory bank controller 9, a parity check node 10, an adder 11 to add a parity bit, a register counter 12 consisting of four sections S8 (i, S3, S4, register a latch 13 consisting of three sections L8,, and Le.
    The buffer memory block 6 (FIG. 3) contains blocks 14 and 15 of 4-K byte memory, selectors 16-19, counters 20 and 21, adder 22 for calculating the address, switch 23, controller 24, allows you to start the sample independently from connections between memory banks and ports. The device can be widely used as a shared memory in a parallel processing system, especially when using a machine, in which the unit of sampling is a page. 5 ill., 1 tab.
    a mat 25 for adding a parity bit; and a parity check node 26.
    The time diagram shows:
    a - signals arriving at the clock input of the device from the output of the master oscillator; B, c, d, e, f — addresses A0, A, Ar AZ, A4 of memory banks MB0, MBf MB4, MB ,, MW;
    g - signals at the output of the register-latch 13; h - shift pulses; 1 - signals from the rear section output
    register counter 12; j - installation enable signal
    addresses;
    k - switching signals from the switch 2 output. The table shows the contents of the hexadecimal counter and the connection between the ports and the memory banks. The device works as follows.
    The addressing device for memory (Fig. 1) contains M ports P0-PM, data input-output, N data banks with MV0do MVICH, and N is a whole multiplier of the specified number M. Switch 2 and counter 1 are used to interconnect ports and memory banks. This system remembers every page of all memory banks. The interconnect bus includes input and output data buses and several control lines. From each port, the address of the page to be sampled is transmitted to the memory bank via the input data bus. On the side of the memory bank, the address in the page is incremented, and the data is entered and output synchronously, due to which many ports have access to
    the same page to read from or write to it continuous data.
    To avoid re-setting the page address on the port side each time the connection between ports and MB0-MB memory banks is switched (|, through switch 2, it is necessary that the page address corresponding to each port in each of the memory banks is MV-MB, transported to a memory bank switched to a specific port.To this end, switch 2 switches sequentially to the right or left and synchronously with this the page address is transported to the next memory bank in the switch direction of the switch. The register counter 12 is used to set and transport the page address.Each memory bank is provided with a latch register 13 for fixing the memory address so that the shift and memory operations can be performed at the same time. to increment the address in the page by one from the memory sample.
    In addition, one page is divided into several blocks, and devices for storing each block are accessible by one periodic repetition of the switching of all memory banks.
    The device provides for the creation of a multiport storage system in which there is a buffer memory block 6 between the switch and each port, and block 6 is configured with an address calculator 22, whereby the page address that is transmitted between the switch and each port is calculated from the sum of counter 1 and the number of each port defined by switch 23, which allows starting sampling regardless of the connection between the memory banks and the ports.
    If the number of memory banks and ports is N (), as shown in FIG. 1, and at the time point the MVh memory bank, and port P; , each
    pages are lengthened and memory management becomes complicated. To eliminate this, the address in the memory is set by the port on a page basis and each page is divided into a plurality of blocks so that the storage device of one block becomes REALIZED to be accessed with one periodic repetition of the memory bank switching, i.e. the sample unit at the time intervals between memory bank switching operations is LB / N, and at some cycle of switching memory banks Lp / Lg, one page data is sampled. If the unit LH / N is too low
    of which is the i-th on the left, connected to each other, then when switching over, there will be no time for the transcom switch 2 in such a way that the page address porting bank between the MB (i + j) modN memory is connected to memory banks. Therefore, the length of Lg by the P port; at the moment of time (.e. ka must satisfy the condition
    during the j-ro switch), it is necessary for the memory bank to transport the page address to the next memory bank on the right side. However, the rightmost memory bank sends the page address to the leftmost memory bank. Assuming that the maximum number of pages that can be remembered is K, the page length is Lp and the block length is L6, we get that the number of bits to be transmitted is given by the expression:
    15
    25
    logzK log2N + log4 (Lp / Le),
    five
    where logjK
    loga (Lp / V
    the number of bits for the page address; the number of bits for the block address in the page;
    log7N is the number of bits to denote the databank to which the access begins. this page is divided into
    With blocks.
    The maximum latency of one port is the time interval between the corresponding switch switch operations, if the memory bank to which access is initiated can be recognized on the port side. If the unit is not taken into account, the port must wait out the data transfer time corresponding to Lp / N . If the page length is shortened to shorten the waiting time, the address
    pages are lengthened and memory management becomes complicated. To eliminate this, the address in the memory is set by the port on a page basis and each page is divided into a plurality of blocks so that the storage device of one block becomes REALIZED to be accessed with one periodic repetition of the memory bank switching, i.e. the sample unit at the time intervals between memory bank switching operations is LB / N, and at some cycle of switching memory banks Lp / Lg, one page data is sampled. If the unit LH / N is too low
    In this case, there will be no time to transport the page address between the memory banks. Therefore, the length Lg of the block must satisfy the condition
    L6 / Nb logiK log2N + logЈ (Lp / / LBjJ + ol,
    where bi is the time interval required for setting the page address on the port side. On each side of the port, a page block must begin with MB, regardless of the memory bank that is being accessed.
    Since the memory bank to which the PSB port is a moment in time is MB (i + j) modN, you only need to refer to the data from Ј (Le / / N (i + j) modN} + l3 to the data (Le / N) Јi + + j) modN + 1 l of this block. To accomplish this, a buffer memory unit 6 is inserted between the switch and each port and the address in block 6 that is accessed from the switch is calculated based on the sum of the value on counter 1 and the value of the port number. It is necessary that the addresses in the block are synchronized from the side of the memory bank and the buffer memory block.
    Memory unit 4 has a capacity of 16 MB (8 bits x 16 million), sections Sg, 4t and S6 + 2, as well as register-counter 12 each have 8 high and low bits of the page address, section S; j ow The 3-bit shift register is used to count the eight blocks that make up one page, and the 32-bit counter 8 is designed to count the 32 bytes that make up one block. In order for the page addresses from sections S6-, and., The block address from section S5 of the counter register 12 to be transported to the memory bank on the right side synchronously with the switching of the switch, the sections SgM and S8.2 of the counter register must have 8- a parallel parallel input for setting the page address; and a 1-bit serial input / output for indicating the memory address in addition to the 8-bit parallel output. Similarly, section S of register counter 12 must also be provided with a 3-bit parallel output and a 1-bit serial input / / output. The section S e of the register-counter 12 must be restored to its original state at the moment when the page address is set, because there are prerequisites
    where the ports are assigned the address on a page basis, and the selection starts from the top of the page. In addition, since it is necessary that after one cycle of viewing all banks of memory, the process proceeds to the next block, a 4-bit section S of register-counter 12 is prepared for counting 16 blocks and its transfer output is connected to the input of section S3. In the case where the buffer storage unit between each port and the switching network is missing, and it is assumed that the sample always starts from the MB0 memory bank, section S may be missing. In this case, the section is incremented by one from the MB memory bank. In addition, to enable access to the page viewport without re-setting the page address for each access, it is necessary to enter transfer signals from sections S, j and Sg.z into section Sg,.
    The eight-bit sections of the LS latch register and the 3-bit L 3 section are used to fix the page address and the block address, which ensures their transfer to the next memory bank and makes it possible to block access to the memory. 5 bits, i.e. thirty-bit, counter 8 is designed to increment the address by one in one block. The page and block addresses must be transmitted to the next memory bank when accessing 32 bytes, or other port and block addresses must be set on the port side.
    Data and addresses are transferred between ports via two 9-bit (8 bits and 1 parity bits) of one-sided buses. The parity check and the addition of parity bit are performed at the input and output of each memory bank using blocks 10 and 11 (Fig. 2).
    Synchronization and permission to write and read are provided by the controller 9 of the memory bank — signals from the master oscillator, sent to the clock input 7 of the device, and a control signal from each port.
    Memory banks with addresses A0, At, Az, A, A4 ... are available from the corresponding ports when pulses are received from the master oscillator of the system. With the aim of
    transferring the page address and the block address to the next memory bank simultaneously with the memory selection of the addresses of the Se sections (, S3 of the register-counter 12 are installed in the sections of the LS latches (, and L e of the register-latch 13, a total of 23 bits, including 16 bits For the address of the page, 3 bits for the block address and 4 times for the bank reference count, they are transmitted for the next memory bank on the right side before transmitting the page address and block address. If all ports start memory sampling in MB0 memory bank, all four digits will not be necessary for the bank reference Otherwise, it is necessary that the contents of the counter 8 for reading the memory bank increase by one when the section S is synchronized. In this case, section 5 of the register-counter 12 must be reset to the initial state at the time of setting the page address, the period for which the address is page can be set from the port side, it is the interval before the beginning of the address shift after the completion of one counting cycle of section S. The time of setting the address is shown in the time diagram in FIG. 4, g. In this case, the switch 2 must be switched synchronously by signals from the giving generator, preferably at the moment of setting the address in the register-latch. This moment is shown in the timing diagram (Fig. 4, k).
    To increase the speed of the device when writing and reading, a block 6 of the buffer memory is entered into it. If a write is made to the MB memory bank starting from the top of the page, it is difficult to determine the beginning of the page at the time of reading, which makes it difficult to sample the page. To eliminate this drawback, it is necessary to determine in advance that the page always starts in a particular memory bank, for example in an MBQ memory bank. In block 6 of the buffer memory
    one
    two blocks 14 and 15 of memory with a capacity of 4 kb are used, creating a device with a double buffer in which another block 15 (or 14) is used to transfer data to the memory bank or from the bank when sampling from block 14 (or 15) . In this case, it is controlled by the switch
    110
    561834Yu
    cheni selectors 16 and 17 on the address
    side and selectors 18 and 19 on the data side to indicate which of blocks 14 or 15 is selected for sampling from the ports or for transmitting data. For example, when memory block 14 is switched and connected by selectors 16 and 18 so that it has a prod. sampling is taken from the upper side of the port, selectors 17 and 19 are switched, and memory block 15 is connected from the memory bank side.
    The data transfer address is 15 out of the five least significant bits A0-A, obtained by frequency-dividing the signal of the master oscillator of the system by the counter 21, the four most significant bits Ae-A5, obtained by adding 20 the port number set by the switch 23, and the gain of the counter 1, the three most significant bits of q, obtained by the frequency division of the signal specifying
    25 of the device generator with a counter 20. Block 4 also contains a controller 24 on the port side, an adder 25 to add a parity bit when writing data from the port side, and a node
    30 26 parity check for data read from the memory bank.
    The use of such a port buffer allows paging from the port side regardless of the connections caused by switch 2, and block 6 calculates the start address of the entry. One page (4 KB) is divided into seven blocks (Fig. 5), each of which is memorized in 32 byte steps in the memory banks in a clockwise direction. For example, in the case of recording from port 4 and when the contents of the hexadecimal counter are O, in accordance with the table, the recording starts in the MB memory bank. When the contents of counter 1 is 1, the recording starts in the MBU memory bank, i.e. the port is connected to the memory bank MB; the number of which is equal to the sum of the contents of the counter and the port number. Consequently, the data of the page to be memorized is transmitted from the port of the memory bank in which recording starts, starting from the first block of the page, and then recording is performed in subsequent memory banks one after the other. Thus, the data at the bottom of the page (the last of its block)
    40
    45
    50
    55
    are recorded in the last memory bank, the first page data sheet is recorded in the first memory bank (for example, MB0). The start address of the recording page is obtained by adding the contents of the hexadecimal counter 1 to the port address, for example, the value 5 in the case of port P. In accordance with this, the start address of the recording can be obtained simply by performing the above calculation at each port.
    The same method is used to read data from the side of the memory bank. Reading begins in the bank, the memory MB; which is connected to the port, and when the read data is written to one of the memory blocks, for example, 15, the port number and the contents of counter 1 are added to the adder 22, and the sum is used as addresses for sampling in block 15, whereby the data read from the memory bank is stored in buffer 15, starting from the top of the page. Accordingly, it is easy to sample in block 15 to read data from there.
    权利要求:
    Claims (1)
    [1]
    Invention Formula
    A memory addressing device containing a counter, a switch, a register-port body, a group of memory blocks and a group of address generators, the first information inputs / outputs of the group's port-registers being information inputs / outputs of the device; The counter is connected to the control input of the switch, the clock input of the counter is connected to the clock input of the device and the clock inputs of the group address drivers, the information inputs / / outputs of the first switch group are connected to the information inputs / / outputs of the corresponding group memory blocks and information inputs of the corresponding group address generators, address outputs of the group address generators are connected to the address inputs of the corresponding group memory blocks, control inputs of the group address generators are connected to the control outputs of the corresponding group memory blocks, each address generator
    5 0 5
    0
    . about 5
    0
    five
    the group contains a register counter, register latch and counter, in each address driver the first-order input and output of the last register-counter output are the input and output of the address-address shifter, respectively, the information output of the register-counter , the bits of the output of the register-latch and bits of the counter are connected to the corresponding bits of the address output of the address former, the counting input of the counter is connected to the clock input of the address former, the control inputs the register counter and latch register are connected to the control input of the address generator, the information input of the register counter is connected to the information input of the address-j generator. sa, the shift output K-th (,, ..., M-1, where M is the number of memory blocks) of the group address generator is connected to the shift input of (K + 1) -th generator (group addresses, output of the M-th shift The group address generator is connected to the shift input of the first group address generator, characterized in that, in order to reduce hardware costs and increase speed by transferring the page address via data lines and calculating the inside-page address for each memory block separately, a group of buffer memory blocks and a group of adders, and the second information inputs / outputs of the group's port-registers are connected to the first information inputs / outputs of the corresponding group buffer blocks, the second information inputs / outputs of which are connected to the corresponding information inputs / / outputs of the second switch group, the first inputs of the group adders are connected to the counter output, the second inputs of the group adders are the corresponding inputs of the device's own device port-addresses, the outputs of the group adders are connected to the first address inputs and the corresponding blocks of the group's buffer memory, the address outputs of the group's port-registers are connected to the second address inputs of the corresponding blocks of the buffer memory of the group, the clock inputs of which are connected to the clock input of the device.
    f "
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    sixteen
    sixteen
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    .5 bit
    -AND
    / 7
    / 7
    21
    I4 14 No. 1SC
     ftoTZl
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    7 From block 1
    Data bus 4 8 bits
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    MB i7
    L0p
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    eight
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    sh

    18
    Sum
    Sh7 Sho
    ffaum
    15
    Vfj boo
    sh
    Vbit
    /


    nineteen
    ъ
    PC
    Wat
    0
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    /
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     8 bit
    25
    26
    / /
     watch out
    -8 bit
    } 96it
    Pue.j
    30 0 2 6 8 W 12 W 16 18 W 22 2 26 28 30 Q Z 29 31 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 1
    a) ЖШЛЛДПЛЛП 4 4 TJlJlJTJTmiJ “M /
    PV0 + PV, 5
    ,
    one
    code
    115 and bytes
    256fl bytes of FIG. five
    类似技术:
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    同族专利:
    公开号 | 公开日
    EP0248906A4|1989-08-22|
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    US4930066A|1990-05-29|
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    法律状态:
    优先权:
    申请号 | 申请日 | 专利标题
    JP60229537A|JPH042976B2|1985-10-15|1985-10-15|
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